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| DS1643 DS1643 Nonvolatile Timekeeping RAM FEATURES PIN ASSIGNMENT NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 * Form, fit, and function compatible with the MK48T08 Timekeeping RAM * Integrated NV SRAM, real time clock, crystal, power- fail control circuit and lithium energy source * Standard JEDEC bytewide 8K x 8 static RAM pinout * Clock registers are accessed identical to the static RAM. These registers are resident in the eight top RAM locations. the absence of power * Totally nonvolatile with over 10 years of operation in * Access times of 120 ns and 150 ns * Quartz accuracy 1 minute a month @ 25C, factory calibrated * BCD coded year, month, date, day, hours, minutes, and seconds with leap year compensation valid up to 2100 28-PIN ENCAPSULATED PACKAGE (700 MIL EXTENDED) * Power-fail write protection allows for 10% VCC power supply tolerance ORDERING INFORMATION DS1643-XXX 28-pin DIP module -120 120 ns access -150 150 ns access DESCRIPTION The DS1643 is an 8K x 8 nonvolatile static RAM with a full function real time clock which are both accessible in a bytewide format. The nonvolatile time keeping RAM is pin and function equivalent to any JEDEC standard 8K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and EEPROM sockets providing read/ write nonvolatility and the addition of the real time clock function. The real time clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and seconds data in 24 hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1643 also contains its own power-fail circuitry which deselects the device when the VCC supply is in an out of tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided. ECopyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. 041697 1/11 DS1643 PIN DESCRIPTION A0-A12 CE OE WE NC VCC GND DQ0-DQ7 - - - - - - - - Address Input Chip Enable Output Enable Write Enable No Connection +5 Volts Ground Data Input/Output CLOCK OPERATIONS-READING THE CLOCK While the double buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1643 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a one is written into the read bit, the seventh most significant bit in the control register. As long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1643 registers are updated simultaneously after the clock status is reset. Updating is within a second after the read bit is written to zero. DS1643 BLOCK DIAGRAM Figure 1 32.768 KHz OSCILLATOR AND CLOCK COUNTDOWN CHAIN CLOCK REGISTERS CE WE 8K X 8 NV SRAM OE + VBAT POWER MONITOR, SWITCHING, AND WRITE PROTECTION POWER GOOD A0-A12 DQ0-DQ7 VCC 041697 2/11 DS1643 DS1643 TRUTH TABLE Table 1 VCC CE VIH X 5 VOLTS 10% VIL VIL VIL <4.5 VOLTS >VBAT The 8-bit of the control register is the write bit. Setting the write bit to a one, like the read bit, halts updates to the DS1643 registers. The user can then load them with the correct day, date and time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the actual clock counters and allows normal operation to resume. running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid (i.e., CE low, OE low, CE2 high, and address for seconds register remain valid and stable). CLOCK ACCURACY The DS1643 is guaranteed to keep time accuracy to within 1 minute per month at 25C. The clock is calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements. The DS1643 does not require additional calibration and temperature deviations will have a negligible effect in most applications. For this reason, methods of field clock calibration are not available and not necessary. Attempts to calibrate the clock that may be used with similar device types (MK48T08 family) will not have any effect even though the DS1643 appears to accept calibration data. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to a 1 stops the oscillator. FREQUENCY TEST BIT Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic "1" and the oscillator is 041697 3/11 DS1643 DS1643 REGISTER MAP - BANK1 Table 2 DATA ADDRESS B7 1FFF 1FFE 1FFD 1FFC 1FFB 1FFA 1FF9 1FF8 - X X X X X OSC W B6 - X X FT X - - R B5 - X - X - - - X B4 - - - X - - - X R X = = B3 - - - X - - - X READ BIT UNUSED B2 - - - - - - - X B1 - - - - - - - X B0 - - - - - - - X FT = YEAR MONTH DATE DAY HOUR MINUTES SECONDS CONTROL 00-99 01-12 01-31 01-07 00-23 00-59 00-59 A FUNCTION OSC = STOP BIT W = WRITE BIT FREQUENCY TEST NOTE: All indicated "X" bits are not dedicated to any particular function and can be used as normal RAM bits. RETRIEVING DATA FROM RAM OR CLOCK The DS1643 is in the read mode whenever WE (write enable) is high and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1643 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. 041697 4/11 DS1643 DATA RETENTION MODE When VCC is within nominal limits (VCC > 4.5 volts) the DS1643 can be accessed as described above by read or write cycles. However, when VCC is below the power-fail point VPF (point at which write protection occurs) the internal clock registers and RAM is blocked from access. This is accomplished internally by inhibiting access via the CE and CE2 signals. When VCC falls below the level of the internal battery supply, power input is switched from the VCC pin to the internal battery and clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal level. INTERNAL BATTERY LONGEVITY The DS1643 has a self contained lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1643 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in the absence of VCC power. The DS1643 is shipped from Dallas Semiconductor with the clock oscillator turned off, so the expected life should be considered to start from the time the clock oscillator is first turned on. Actual life expectancy of the DS1643 will be much longer than 10 years since no internal lithium battery energy is consumed when VCC is present. In fact, in most applications, the life expectancy of the DS1643 will be approximately equal to the shelf life (expected useful life of the lithium battery with no load attached) of the lithium battery which may prove to be as long as 20 years. 041697 5/11 DS1643 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C -20C to +70C 260C for 10 seconds (See Note 7) * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Supply Voltage Logic 1 Voltage All Inputs Logic 0 Voltage All Inputs SYMBOL VCC VIH VIL MIN 4.5 2.2 -0.3 TYP 5.0 MAX 5.5 VCC+0.3 0.8 UNITS V V V (0C to 70C) NOTES 1 DC ELECTRICAL CHARACTERISTICS PARAMETER Average VCC Power Supply Current TTL Standby Current (CE = VIH, CE2 = VIL) CMOS Standby Current (CE=VCC-0.2V, CE2=GND+0.2V) Input Leakage Current (any input) Output Leakage Current Output Logic 1 Voltage (IOUT = -1.0 mA) Output Logic 0 Voltage (IOUT = +2.1 mA) Write Protection Voltage SYMBOL ICC1 ICC2 ICC3 IIL IOL VOH VOL VTP 4.0 4.25 -1 -1 2.4 3 2 MIN TYP (0C tA 70C; VCC = 5.0V 10%) MAX 65 6 4.0 +1 +1 UNITS mA mA mA A A V 0.4 4.5 V V NOTES 2, 3 2, 3 2, 3 041697 6/11 DS1643 AC ELECTRICAL CHARACTERISTICS DS1643-120 PARAMETER Read Cycle Time Address Access Time CE and CE2 Access Time CE and CE2 Data Off Time Output Enable Access Time Output Enable Data Off Time Output Enable to DQ Low-Z CE and CE2 to DQ Low-Z Output Hold from Address Write Cycle Time Address Setup Time CE and CE2 Pulse Width Address Hold from End of Write Write Pulse Width WE Data Off Time WE or CE Inactive Time Data Setup Time Data Hold Time High SYMBOL tRC tAA tCEA tCEZ tOEA tOEZ tOEL tCEL tOH tWC tAS tCEW tAH1 tAH2 tWEW tWEZ tWR tDS tDH1 tDH2 10 85 0 15 5 5 5 120 0 100 5 30 120 40 10 110 0 15 MIN 120 120 120 40 100 35 5 5 5 150 0 120 5 30 150 MAX MIN 150 (0C to 70C; VCC = 5.0V 10%) DS1643-150 MAX UNITS ns 150 150 50 120 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 50 ns ns ns ns ns 5 6 5 6 NOTES AC TEST CONDITIONS Input Levels: Transition Times: 0V to 3V 5 ns CAPACITANCE PARAMETER Capacitance on all pins (except DQ) Capacitance on DQ pins SYMBOL CI CDQ MIN TYP MAX 7 10 UNITS pF pF (tA = 25C) NOTES 041697 7/11 DS1643 AC ELECTRICAL CHARACTERISTICS (POWER-UP/DOWN TIMING) PARAMETER CE2, CE or WE at VIH before Power Down VPF (Max) to VPF (Min) VCC Fall Time VPF (Min) to VSO VCC Fall Time VSO to VPF (Min) VCC Rise Time VPF (Min) to VPF (Max) VCC Rise Time Power-Up Expected Data Retention Time (Oscillator On) SYMBOL tPD tF tFB tRB tR tREC tDR MIN 0 300 10 1 0 15 10 25 35 TYP MAX UNITS s s s s s ms years (0C to 70C) NOTES 4 DS1643 READ CYCLE TIMING READ tRC A0-A12 tAA tCEA CE tCEL OE tOEA tAS tAH READ tRC WRITE tWC tWR tWEW WE tOEL tOH DQ0-DQ7 VALID OUT VALID OUT VALID IN tOEZ 041697 8/11 DS1643 DS1643 WRITE CYCLE TIMING WRITE tWC A0-A12 tAS tAH2 tWR tCEW tAA tAH1 WRITE tWC READ tRC CE tOEA OE tWR tWEW WE tDH1 tCEZ DQ0- DQ7 VALID OUT tDS VALID IN tDH2 tDS VALID IN tWEZ VALID OUT POWER-DOWN/POWER-UP TIMING VCC VPF (MAX) VPF (MIN) VPF tF tR tFB VSO VSO tRB tPD tREC CE IBATT DATA RETENTION tDR 041697 9/11 DS1643 NOTES: 1. All voltages are referenced to ground. 2. Typical values are at 25C and nominal supplies. 3. Outputs are open. 4. Data retention time is at 25C and is calculated from the date code on the device package. The date code XXYY is the year followed by the week of the year in which the device was manufactured. For example, 9225, would mean the 25th week of 1992. 5. tAH1, tDH1 are measured from WE going high. 6. tAH2, tDH2 are measured from CE going high. 7. Real-Time Clock Modules can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. OUTPUT LOAD +5 VOLTS 1.8K D.U.T. 1K 100 pF 041697 10/11 DS1643 DS1643 28-PIN PACKAGE PKG DIM A IN. MM B IN. MM A C IN. MM D IN. MM E IN. MM C F IN. MM 28-PIN MIN 1.470 37.34 0.675 17.75 0.335 8.51 0.075 1.91 0.015 0.38 0.140 3.56 0.090 2.29 0.590 14.99 0.010 0.25 0.015 0.43 MAX 1.490 37.85 0.740 18.80 0.355 9.02 0.105 2.67 0.030 0.76 0.180 4.57 0.110 2.79 0.630 16.00 0.018 0.45 0.025 0.58 1 F D K G G IN. MM H IN. MM J IN. MM K IN. MM J E H B 041697 11/11 |
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